A memory device having a three-dimensional structure has been proposed in which memory holes are made in a stacked body in which inter-electrode layer insulating layers are multiply stacked alternately with electrode layers that function as control gates of memory cells, and silicon bodies used to form channels are provided on the side walls of the memory holes with a charge storage film interposed between the silicon bodies and the side walls.
Although anisotropic etching such as, for example, RIE (Reactive Ion Etching), etc., is used to make the holes, the diameters of the holes may fluctuate in the depth direction. In particular, it becomes difficult to make a hole with a uniform diameter when the number of layers of the electrode layers is increased and the aspect ratio of the hole is high. The fluctuation in the depth direction of the diameters of the holes may cause fluctuation of the characteristics of the memory cell transistors.